DocumentCode
2782400
Title
SRAM Variability and Supply Voltage Scaling Challenges
Author
Kapre, R. ; Shakeri, K. ; Puchner, H. ; Tandigan, J. ; Nigam, T. ; Jang, K. ; Reddy, M.V.R. ; Lakshminarayanan, S. ; Sajoto, D. ; Whately, M.
Author_Institution
Cypress Semicond., San Jose, CA
fYear
2007
fDate
15-19 April 2007
Firstpage
23
Lastpage
28
Abstract
We have developed a methodology for SRAM cell design that unifies all the major design criterion - cell stability, write margin, read speed and leakage into a single metric. This metric has been used to design a 65nm cell while accounting for challenges posed by increased Vt variability, Vcc scaling and NBTI drift. The impact of NBTI drift on the periphery of a high speed SRAM has been simulated and measured
Keywords
SRAM chips; high-speed integrated circuits; integrated circuit reliability; memory architecture; 65 nm; NBTI drift; SRAM cell design; cell stability; high speed SRAM; read speed; supply voltage scaling; write margin; Contact resistance; Degradation; MOSFETs; Niobium compounds; Random access memory; SRAM chips; Stability criteria; Testing; Threshold voltage; Titanium compounds; Cell Stability; NBTI; SRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location
Phoenix, AZ
Print_ISBN
1-4244-0919-5
Electronic_ISBN
1-4244-0919-5
Type
conf
DOI
10.1109/RELPHY.2007.369863
Filename
4227604
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