• DocumentCode
    2782733
  • Title

    Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration

  • Author

    Cheng, Yi Lung ; Lin, B.L. ; Lee, S.Y. ; Chiu, C.C. ; Wu, Kenneth

  • Author_Institution
    Technol. Quality & Reliability Div., Taiwan Semicond. Manuf. Co., Hsinchu
  • fYear
    2007
  • fDate
    15-19 April 2007
  • Firstpage
    128
  • Lastpage
    133
  • Abstract
    Sub-micron Cu damascene interconnect, electromigration is mainly due to the diffusion at the interfaces of Cu with liner or dielectric capping layer. Many reports have pointed out the Cu/capping dielectric as the dominant interface. Experiments were performed to study the effect of the Cu line width and stress current direction on electromigration. For Cu line with multiple via connections, the resistance to electromigration is influenced by the metal width regardless of the electron flow direction. On the other hand, in case of a single via connection structure, the results revealed significant differences in electromigration behavior for up-stream and down-stream stress. For the up-stream stress, EM behavior is dominated by Cu drift velocity. Wider metal lines have the lower Cu drift velocity, and so possess the better EM resistance. In the case of down-stream stress, two distinct failure modes, via bottom and metal line depletion, were found, thus worsening the lifetime distribution due to higher current in the via bottom for the wider metal. Two effective methods, enlarging via size and enhancing Cu/capping process, were demonstrated to improve the EM distribution in this study
  • Keywords
    copper; electromigration; failure analysis; integrated circuit interconnections; life testing; 65 nm; Cu; Cu interconnect width effect; Cu/capping dielectric; EM resistance; dielectric capping layer; down-stream stress electromigration; drift velocity; electron flow direction; failure modes; lifetime distribution; metal line depletion; multiple via connections; stress current direction; submicron Cu damascene interconnect; up-stream stress; via bottom; via size; Circuit testing; Current density; Dielectrics; Electromigration; Electron mobility; Integrated circuit interconnections; Plasma temperature; System testing; Thermal conductivity; Thermal stresses; 65nm technology; Current direction; Drift velocity; Electromigration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
  • Conference_Location
    Phoenix, AZ
  • Print_ISBN
    1-4244-0919-5
  • Electronic_ISBN
    1-4244-0919-5
  • Type

    conf

  • DOI
    10.1109/RELPHY.2007.369881
  • Filename
    4227622