DocumentCode :
278340
Title :
Designer fault models for VLSI
Author :
Dunn, Mark
Author_Institution :
Dept. of Comput. Sci., Sheffield Univ., UK
fYear :
1991
fDate :
33374
Firstpage :
42461
Lastpage :
42465
Abstract :
Describes a simple abstract specification formalism for a functional block, describes some of the properties of these specifications and their relationship to the design process. The author looks at a simple description of what `faulty´ means and describes what a fault model is in terms of his simple abstract specification. Using this framework, he then describes various fault models, showing that new fault models can assist in the design process. This is an example of the power of formal specification. It helps demonstrate that something is over specified. In fact, the new fault models help to highlight the over specification that occurs early in circuit design process
Keywords :
VLSI; circuit CAD; digital integrated circuits; integrated circuit testing; logic CAD; specification languages; VLSI; abstract specification formalism; circuit design process; design for testability; design process; designer fault models; formal specification; functional block; over specification;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Design for Testability, IEE Colloquium on
Conference_Location :
London
Type :
conf
Filename :
181575
Link To Document :
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