Test for designability-a new architecture for VLSI testers

In recent years, there has been much discussion and effort expended in the area of Design-for-Testability with advances in fault modelling and test strategies such as the IEEE standard for scan test. This paper shows how the recognition of these trends led Schlumberger to introduce a new generation of VLSI testers which eases the design-to-test interface through the design of a new timing architecture which much more closely resembles the event-driven nature of simulator timing. Now designers are not limited by the necessity of having to run the simulator digital stimulus through a restrictive `Tester Constraints´ filter which is nearly always the case with the old format-style cycle-drive tester architecture