Dual-Phase Line-Based QCA Memory Design

This paper describes a line-based, parallel-access QCA memory design that is synchronized by a dual-phase clocking scheme. In line-based QCA memories, data bits are stored propagating along acyclic QCA lines and additional clock generators are used to create the clocking zones of the memory regions. The memory design proposed in this paper requires an easy-to-implement, dual-phase clocking scheme. Dual-phase clocking is implemented with two clock phases which have the same duty cycle and are phase-shifted by half a clock cycle, thus, requiring only one additional clock generator. The number of clock zones per memory cell is reduced to a minimum of two, permitting denser memory implementations.