Title :
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding
Author :
Lechner, Jakob ; Lampacher, Martin ; Polzer, Thomas
Author_Institution :
Inst. of Comput. Eng., Vienna Univ. of Technol., Vienna, Austria
Abstract :
This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.
Keywords :
asynchronous circuits; delays; dual codes; error correction codes; error detection codes; fault diagnosis; fault tolerance; integrated circuit interconnections; logic design; 4-phase dual rail code; GALS-systems; asynchronous circuit design; coding efficiency; data transmission; data word processing; delay-insensitive code; error correcting codes; error detecting codes; fault model; fault tolerance; four-phase dual-rail coding; information redundancy; interconnect architecture; interconnect resource; metastable upset; robust asynchronous interfacing scheme; single-bit errors; system timing; variation tolerance; Circuit faults; Delay; Encoding; Integrated circuit interconnections; Protocols; Receivers; Registers; Asynchronous circuits; Delay-insensitivity; Error correcting codes; Fault-tolerance; GALS; Metastability;
Conference_Titel :
Application of Concurrency to System Design (ACSD), 2012 12th International Conference on
Conference_Location :
Hamburg
Print_ISBN :
978-1-4673-1687-3
DOI :
10.1109/ACSD.2012.29