Title :
A structured approach to architectural yield optimisation for WSI
Author_Institution :
Div. Electr. & Electron. Eng., Hatfield Polytech., UK
Abstract :
The paper is based on the author´s experience of modelling the yield of the Aspex Microsystems-Brunel University WSI Associative Processor (WASP) device as it has evolved from early studies some six years ago, through a number of test chips and concept demonstrator ULSI and WSI devices to future WSI prototypes. The tenet of the paper is that the research, development, and production phases of WSI design have different yield modelling requirements. Accordingly, a different method for device yield evaluation is proposed and demonstrated for each of the above stages
Keywords :
VLSI; computer architecture; microprocessor chips; Aspex Microsystems-Brunel University WSI Associative Processor; ULSI; WASP; WSI devices; WSI prototypes; architectural yield optimisation; production phases; test chips; yield; yield evaluation; yield modelling requirements;
Conference_Titel :
Wafer Scale Integration, IEE Colloquium on
Conference_Location :
London
