DocumentCode
2784242
Title
Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes
Author
Ker, Ming-Dou ; Wang, Chang-Tzu ; Tang, Tien-Hao ; Su, Kuan-Cheng
Author_Institution
Inst. of Electron., National Chiao-Tung Univ., Hsinchu
fYear
2007
fDate
15-19 April 2007
Firstpage
594
Lastpage
595
Abstract
A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.
Keywords
CMOS integrated circuits; detector circuits; electrostatic discharge; 0.13 micron; 1.2 V; CMOS processes; ESD detection circuit; ESD protection; mixed-voltage I/O interfaces; power-rail ESD clamp circuit; power-rail electrostatic discharge clamp circuit; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; Low voltage; Microelectronics; Power system reliability; Protection; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location
Phoenix, AZ
Print_ISBN
1-4244-0919-5
Electronic_ISBN
1-4244-0919-5
Type
conf
DOI
10.1109/RELPHY.2007.369967
Filename
4227708
Link To Document