DocumentCode :
2784630
Title :
Characterization of Degradation of 65nm Node via Chains and Single Vias
Author :
Federspiel, X. ; Courtas, S. ; Gregoire, M.
Author_Institution :
CR & D labs, NXP Semicond., Crolles
fYear :
2007
fDate :
15-19 April 2007
Firstpage :
640
Lastpage :
641
Abstract :
We used the resistance increase of single via to determine the intrinsic degradation kinetics of via in the temperature range 175 to 325C. The evolution of resistance in time follows a parabolic regime up to 325C, with activation energy of 1.0eV. It is worth noting that the evolution of degradation kinetics with temperature follows a simple Arrhenius equation. Thus, there is no evidence for an effect of thermo elastic stress on the degradation kinetics. We showed that the degradation mechanism in chains and single vias is similar. It is also noticeable that we found a bimodal distribution of resistance increase that is not visible from measurement of via chains. Together with making FA easier, this demonstrates the benefit of using single via to characterize stress voiding.
Keywords :
failure analysis; integrated circuit interconnections; integrated circuit measurement; 1.0 eV; 175 to 325 C; 65 nm; Arrhenius equation; bimodal distribution; intrinsic degradation kinetics; single vias; stress voiding; via chains; Copper; Degradation; Electrical resistance measurement; Failure analysis; Kelvin; Kinetic theory; Microelectronics; Temperature distribution; Temperature measurement; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location :
Phoenix, AZ
Print_ISBN :
1-4244-0919-5
Electronic_ISBN :
1-4244-0919-5
Type :
conf
DOI :
10.1109/RELPHY.2007.369990
Filename :
4227731
Link To Document :
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