Title :
Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems
Author_Institution :
Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany
Abstract :
Current schedulability analyses for preemptive systems consider cache behaviour by adding preemption-caused cache reload costs. Thereby, they ignore the fact that delays due to cache misses often have a reduced impact because of pipeline effects. In this paper, these methods are called isolated. Pipeline-related preemption costs are not considered at all in current schedulability analyses. This paper presents two cache- and pipeline-sensitive response time analysis methods for fixed-priority preemptive scheduling. The first is an isolated method. The second method incorporates the preemption-caused cache costs into the worst-case execution time (WCET) of the preempted task. This allows for the compensation of delays due to cache misses by pipeline effects. It is shown that the applicability of isolated approaches is limited to a certain class of CPUs. Practical experiments are used to compare both methods
Keywords :
cache storage; compensation; delays; pipeline processing; processor scheduling; real-time systems; cache misses; cache-sensitive fixed-priority scheduling; delay compensation; fixed-priority preemptive scheduling; isolated methods; pipeline-related preemption costs; pipeline-sensitive fixed-priority scheduling; preemption-caused cache reload costs; preemptive real-time systems; response time analysis methods; schedulability analysis; worst-case execution time; Computer science; Costs; Delay effects; Hardware; Interference; Pipelines; Prefetching; Processor scheduling; Real time systems; Throughput;
Conference_Titel :
Real-Time Systems Symposium, 2000. Proceedings. The 21st IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-0900-2
DOI :
10.1109/REAL.2000.896009