Title :
RC-tree delay evaluation in hierarchical environment
Author :
Mheir-El-Saadi, Farid ; Kaminska, Bozena
Author_Institution :
Ecole Polytech. de Montreal, Que., Canada
Abstract :
An algorithm is presented to compute the delay of an RC-tree network in a hierarchical manner. The RC-tree model is derived from the work of J. Rubinstein and P. Penfield (1983) and T.M. Lin and C. Mead (1984). User-defined storage space, called properties, are used to store partial delay results in the design hierarchy. The delay evaluation becomes very CPU time efficient. This algorithm is well adapted for the evaluation of interconnect wire delay in a hierarchical delay analysis tool. It has been implemented in the authors´ hierarchical analysis tool, PREDICT
Keywords :
circuit analysis computing; delays; distributed parameter networks; linear network analysis; passive networks; PREDICT; RC-tree delay evaluation; RC-tree network; design hierarchy; hierarchical delay analysis tool; hierarchical environment; interconnect wire delay; Central Processing Unit; Circuit analysis; Databases; Delay effects; Failure analysis; Information analysis; Integrated circuit interconnections; Switching circuits; Timing; Wire;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140665
