Design and FPGA implementation of digit-serial FIR filters

Author

Dawoud, D.S. ; Masupe, S.

Author_Institution

Natal Univ., Durban

Volume

1

fYear

2004

fDate

17-17 Sept. 2004

Firstpage

203

Abstract

The design of a digit-serial N-tap FIR filter with programmable coefficients is presented. The design considers the general case of a W-bit sample word and an M-bit coefficient word. The processing of the data within the filter takes place with full precision. The output data is truncated to W bits. The design introduces a new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements. Sign-amplitude representation for the coefficients and two´s complement for the input samples simplifies the circuit configuration and allows the use of one common two´s complement circuit for all the filter section. A 100-tap, 8-bit word length version filter is implemented using an Altera FPGA device. The filter can be used in real-time processing with sample rate range from 7.5 to 22 MHz

Keywords

FIR filters; digital arithmetic; field programmable gate arrays; integrated circuit design; logic design; multiplying circuits; Altera FPGA device; M-bit coefficient word; W-bit sample word; digit-serial FIR filters; digit-serial multiplier; processing time; programmable coefficients; sign-amplitude representation; twos complement circuit; Arithmetic; Circuits; Clocks; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware; Logic design; Real time systems; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

AFRICON, 2004. 7th AFRICON Conference in Africa

Conference_Location

Gaborone

Print_ISBN

0-7803-8605-1

Type

conf

DOI

10.1109/AFRICON.2004.1406659

Filename

1406659