DocumentCode
2786752
Title
DSynth: A Pipeline Synthesis Environment for FPGAs
Author
Wirthlin, Michael ; Sun, Welson
Author_Institution
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT
fYear
2006
fDate
24-26 April 2006
Firstpage
343
Lastpage
344
Abstract
A synthesis environment called DSynth has been created for synthesizing high-performance pipelined circuits for FPGAs from synchronous data flow specifications. The goal of this work is to generate the minimum size circuit that meets the throughput constraint of the data flow model. To achieve this constraint efficiently, this approach relies heavily upon a library of pre-characterized pipelined circuit modules. In addition, resource sharing is used extensively to reduce the overall hardware cost
Keywords
data flow graphs; field programmable gate arrays; high level synthesis; integrated circuit design; pipeline processing; DSynth method; FPGA; high-performance pipelined circuits; pipeline synthesis; pipelined circuit modules; resource sharing; synchronous data flow specifications; Circuit synthesis; Costs; Field programmable gate arrays; Libraries; Mathematical model; Pipelines; Resource management; Signal synthesis; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on
Conference_Location
Napa, CA
Print_ISBN
0-7695-2661-6
Type
conf
DOI
10.1109/FCCM.2006.37
Filename
4020951
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