Mapping a real-time video algorithm to a context-switched FPGA

Author

Kelem, Steven

Author_Institution

Xilinx Inc., San Jose, CA, USA

fYear

1997

fDate

16-18 Apr 1997

Firstpage

236

Lastpage

237

Abstract

This paper describes the implementation of a real-time video algorithm on a context-switched FPGA. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. The algorithm makes use of special features of this architecture to achieve high utilization of the silicon at run time. Two configuration planes are programmed as distributed RAM and two planes perform replications of the calculation in parallel. The interplay between the CLB architecture, communication between configuration planes, context-switching overhead, and the end-user application are examined as we map the algorithm onto this architecture

Keywords

field programmable gate arrays; logic design; CLB architecture; Xilinx XC4000E; configuration planes; context-switched FPGA; context-switching; end-user; real-time video algorithm; state saving; time-multiplexing; Algorithm design and analysis; Clocks; Field programmable gate arrays; Hardware; Image restoration; Logic arrays; Logic devices; Random access memory; Read-write memory; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8159-4

Type

conf

DOI

10.1109/FPGA.1997.625366

Filename

625366