DocumentCode :
2787269
Title :
PEPSC: A Power-Efficient Processor for Scientific Computing
Author :
Dasika, Ganesh ; Sethia, Ankit ; Mudge, Trevor ; Mahlke, Scott
Author_Institution :
ARM R&D, Austin, TX, USA
fYear :
2011
fDate :
10-14 Oct. 2011
Firstpage :
101
Lastpage :
110
Abstract :
The rapid advancements in the computational capabilities of the graphics processing unit (GPU) as well as the deployment of general programming models for these devices have made the vision of a desktop supercomputer a reality. It is now possible to assemble a system that provides several TFLOPs of performance on scientific applications for the cost of a high-end laptop computer. While these devices have clearly changed the landscape of computing, there are two central problems that arise. First, GPUs are designed and optimized for graphics applications resulting in delivered performance that is far below peak for more general scientific and mathematical applications. Second, GPUs are power hungry devices that often consume 100-300 watts, which restricts the scalability of the solution and requires expensive cooling. To combat these challenges, this paper presents the PEPSC architecture - an architecture customized for the domain of data parallel scientific applications where power-efficiency is the central focus. PEPSC utilizes a combination of a two-dimensional single-instruction multiple-data (SIMD) data path, an intelligent dynamic prefetching mechanism, and a configurable SIMD control approach to increase execution efficiency over conventional GPUs. A single PEPSC core has a peak performance of 120 GFLOPs while consuming 2W of power when executing modern scientific applications, which represents an increase in computation efficiency of more than 10X over existing GPUs.
Keywords :
computer architecture; graphics processing units; laptop computers; parallel machines; storage management; GPU; PEPSC architecture; SIMD data path; desktop supercomputer; general programming models; graphics processing unit; high-end laptop computer; intelligent dynamic prefetching mechanism; power-efficient processor; scientific computing; single-instruction multiple-data data path; Benchmark testing; Computer architecture; Graphics processing unit; Hardware; Pipelines; Prefetching; GPGPU; Low power; SIMD; Scientific computing; Throughput computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on
Conference_Location :
Galveston, TX
ISSN :
1089-795X
Print_ISBN :
978-1-4577-1794-9
Type :
conf
DOI :
10.1109/PACT.2011.16
Filename :
6113792
Link To Document :
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