Building Retargetable and Efficient Compilers for Multimedia Instruction Sets

Multimedia Instruction Sets have been introduced more than 20 years ago to speedup multimedia processing on General Purpose Processors. However, to take advantage of these instructions, developers have to cope with the low-level assembly or the equivalent C interfaces, which hinders code portability and raises development cost increases. An alternative is to let the compiler automatically generate optimized versions: ICC generates relatively efficient code for its supported platforms but does not target other processors. On the other hand, GCC targets a wide range of devices but generates less efficient code. In this paper, we present a retargetable compiler infrastructure for SIMD architectures based on three key points: a generic Multimedia Instruction Set, the combination of loop vectorization transformations with Super-word Level Parallelism and memory transfer optimizations. Three compilers, for SSE, AVX and NEON have been built using this common infrastructure.