Compiler Directed Data Locality Optimization for Multicore Architectures

Emerging multicore architectures differ from prior multi- processor based systems in that they typically employ on- chip cache hierarchies where subsets of caches are shared by subsets of cores. This cache sharing can result in opportunities as well as problems in a multithreaded execution, depending on how compatible the data access and data sharing patterns exhibited by threads are with the physical cache sharing imposed by the underlying architecture. Investigating this relationship and exploiting it to improve application performance through program transformation are the main objectives of this paper.