• DocumentCode
    2787498
  • Title

    Mixed-radix Twisted Torus Interconnection Networks

  • Author

    Camara, J.M. ; Moretó, Miquel ; Vallejo, Enrique ; Beivide, Ramó ; Miguel-Alonso, José ; Martinez, Carmen ; Navaridas, Javier

  • Author_Institution
    Dept. of Electromech. Eng., Univ. of Burgos
  • fYear
    2007
  • fDate
    26-30 March 2007
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    Many parallel computers use Tori interconnection networks. Machines from Cray, HP and IBM, among others, exploit these topologies. In order to maintain full network symmetry, 2D and 3D Tori must have the same number of nodes (k) per dimension resulting in square or cubic topologies. Nevertheless, for practical reasons, computer engineers have designed and built 2D and 3D Tori having a different number of nodes per dimension. These mixed-radix topologies are not edge-symmetric which translates into poor performance provoked by an unbalanced use of the network links. In this paper, we propose and analyze twisted 2D and 3D Tori which remove the network bottlenecks present in mixed-radix standard Tori. These new topologies recover edge-symmetry and, consequently, balance the utilization of their links. We describe the distance-related parameters of these twisted networks and use simulation to asses their performance under synthetic loads. The obtained results show noticeable and consistent performance gains. In addition, we propose scalable and practicable packet routing and folding techniques for these interconnection subsystems. The complexity of the resulting architectural solutions is similar to the one exhibited by traditional routing and folding mechanisms employed in standard Tori. This fact together with the performance improvements obtained could justify the use of these twisted topologies in the future.
  • Keywords
    multiprocessor interconnection networks; network routing; parallel machines; distance-related parameters; mixed-radix twisted Tori interconnection networks; packet routing; Computer architecture; Computer networks; Concurrent computing; Design engineering; Hypercubes; Maintenance engineering; Multiprocessor interconnection networks; Network topology; Performance gain; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
  • Conference_Location
    Long Beach, CA
  • Print_ISBN
    1-4244-0910-1
  • Electronic_ISBN
    1-4244-0910-1
  • Type

    conf

  • DOI
    10.1109/IPDPS.2007.370270
  • Filename
    4227998