Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments

Author

Hassan, Syed Minhaj ; Choudhary, Dhruv ; Rasquinha, Mitchelle ; Yalamanchili, Sudhakar

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

10-14 Oct. 2011

Firstpage

187

Lastpage

188

Abstract

The presence of multiple MCs and their integration into the on-chip network fabric creates a highly concurrent system that can support significant levels of memory level parallelism (MLP) across cores. This work exposes the trade-off between DRAM parameters, bank level parallelism (BLP), and row buffer hit rate that exposes the amount of effective BLP that is necessary to approximate a 100% hit rate. We further study how this trade-off can be controlled and propose a class of global (system) and local (within an MC) address mappings that can be tuned to optimize the performance across a set of multiprogrammed benchmarks.

Keywords

DRAM chips; buffer storage; parallel memories; parallel processing; BLP; DRAM parameter; MLP; bank level parallelism; locality vs. parallelism tradeoff; memory level parallelism; multiple memory controller environment; on-chip network; row buffer hit rate; Bandwidth; Benchmark testing; Computer architecture; Education; Parallel processing; Random access memory; System-on-a-chip; Address Mapping; Bank Level Parallelism; DRAM; Row Buffer Hit Rate;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on

Conference_Location

Galveston, TX

ISSN

1089-795X

Print_ISBN

978-1-4577-1794-9

Type

conf

DOI

10.1109/PACT.2011.33

Filename

6113808