Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy

An inclusive cache hierarchy is commonly used in Chip Multiprocessors (CMPs) to simply cache coherence. How- ever, inclusive caches have limited performance due to the fact that all cache blocks in the higher level caches (referred as core caches) should be a subset of the last-level cache (LLC). When the sum of the sizes of the core caches is comparable to that of the LLC, cache performance is poor due to low cache capacity. Moreover, when a cache block is evicted from the LLC, it must be invalidated from all the core caches, referred as an inclusion victim. Nevertheless, due to the fact that temporal locality is hidden by core caches, blocks that have high temporal locality in the core caches tend to become replacement candidates in the LLC. In this case, the highly-accessed blocks in the core caches are evicted from core caches to cause cache misses and harm the cache performance. Based on our experiments, in a 2- core inclusive CMP, 73.57% of inclusion victims will be re-referenced within 4 LI misses in the corresponding sets after their invalidations (4 is the LI cache associativity). It would be promising if there were an inclusive cache management policy that could decrease the number of hot inclusion victims and potentially increase the capacity of the cache hierarchy. Thus, we propose the Sampling Temporal Touch Hint Inclusive Cache Management Policy.