DMA controller design using self-clocked methodology

Asynchronous sequential circuits offer improved speed of operation when compared to their synchronous counterparts. A number of new design methodologies which involve locally generating a clock and using it to self synchronize the machine have been proposed. Such clock signals are generated whenever an input changes, or by controlled excitation whenever a change of inputs necessitates a change of state. All such designs, where the circuit is timed by locally generated clocks, are called self-clocked sequential circuits. This paper uses a design methodology for the state variable toggling through data driven clocks to implement a direct memory access controller (DMAC) as a design example. The design is simulated in software and also implemented using discrete hardware components. The methodology can be extended to parallel controllers for neural networks and automated using state assignment techniques already developed for synchronous parallel controllers