Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency

A 45nm microprocessor integrates an all-digital dynamic variation monitor (DVM), consisting of a tunable replica circuit with a time-to-digital converter, to measure the impact of dynamic variations on path-level delay or frequency. Measurements reveal the high sensitivity of the microprocessor maximum clock frequency (F_MAX) to the placement and magnitude of a high-frequency supply voltage (V_CC) droop and demonstrate the DVM capability of tracking F_MAX changes to within 1% for a wide range of V_CC droop profiles. Furthermore, the DVM interfaces with an adaptive clock control circuit to dynamically change the clock frequency in response to dynamic variations, enabling the microprocessor to operate at maximum efficiency.