Author :
Van der Plas, Geert ; Thijs, Steven ; Linten, Dimitri ; Katti, Guruprasad ; Limaye, Paresh ; Mercha, Abdelkarim ; Stucchi, Michele ; Oprins, Herman ; Vandevelde, Bart ; Minas, Nikolas ; Cupac, Miro ; Dehan, Morin ; Nelis, Marc ; Agarwal, Rahul ; Dehaene,
Abstract :
We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5μm diameter at 10μm pitch Cu-TSV. We investigate electrical, thermal and thermo-mechanical issues encountered in 3D. The electrical yield and ESD of TSVs is reviewed and designers are advised how to ensure yield and reliability. For thermal and thermo-mechanical we´ll indicate based on experimental characterization, the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow which leverages information captured by smart samples.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; 3D CMOS technology; 3D stack-challenges; ESD; TSV; chip package co-design flow; chip stack; electrical yield; electrical/thermal/thermo-mechanical behavior; experimental characterization; size 130 nm; thermo-mechanical simulations; Electrostatic discharge; Monitoring; Solid modeling; Stress; Thermomechanical processes; Three dimensional displays; Through-silicon vias;
