DocumentCode :
2788220
Title :
Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems
Author :
Yang, Yi-Hua E. ; Prasanna, Viktor K.
Author_Institution :
Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2011
fDate :
10-14 Oct. 2011
Firstpage :
424
Lastpage :
433
Abstract :
Conventionally, regular expression matching (REM) has been performed by sequentially comparing the regular expression (regex) to the input stream, which can be slow due to excessive backtracking [21]. Alternatively, the regex can be converted to a deterministic finite automaton (DFA) for efficient matching, which however may require an extremely large state transition table (STT) due to exponential state explosion [17, 27]. We propose the segmented regex-NFA (SR-NFA) architecture, where the regex is first compiled into modular nondeterministic finite automata (NFA), then partitioned, optimized, and matched efficiently on modern multi-core processors. SR-NFA offers attack-resilient multi-gigabit per second matching throughput, does not suffer from either backtracking or state explosion, and can be rapidly constructed. For regex sets that construct a DFA with moderate state explosion, i.e., on average 200k states in the STT, the proposed SR-NFA is 367k times faster to construct and update and use 23k times less memory than the DFA approach. Running on an 8-core 2.6 GHz Opteron platform, our prototype achieves 2.2 Gbps average matching throughput for regex sets with up to 4,000 SR-NFA states per regex set.
Keywords :
backtracking; finite automata; multiprocessing systems; SR-NFA architecture; attack-resilient multigigabit per second; backtracking; deterministic finite automaton; exponential state explosion; large state transition table; modular nondeterministic finite automata; multicore processor; multicore system; regular expression matching; Automata; Complexity theory; Doped fiber amplifiers; Explosions; Multicore processing; Throughput; Vectors; NFA; Regular expression; bit-level parallelism; multi-core processor; thread-level parallelism;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on
Conference_Location :
Galveston, TX
ISSN :
1089-795X
Print_ISBN :
978-1-4577-1794-9
Type :
conf
DOI :
10.1109/PACT.2011.73
Filename :
6113850
Link To Document :
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