A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS

This paper presents the design rationale and measured results of a low power, low jitter, PVT-stable FBAR-based RF synthesizer implemented in 0.13μm CMOS. A digitally controlled FBAR oscillator, tuned with a switched-capacitor array, provides 5800ppm of frequency tuning, sufficient to cover a wide range of manufacturing and temperature variations of an FBAR. An all-digital phase-locked loop (ADPLL) is used to stabilize the FBAR DCO. In the ADPLL architecture, we introduce a two-stage time-to-digital converter (TDC) to detect phase differences between reference and divider clocks. The solution offers a fine TDC resolution without large and power-hungry TDC circuitry typically used to address in-band phase noise requirements. With the tuning range, the power consumption of 2.8 mW, and an integrated RMS jitter of 0.38ps from 10kHz to 20MHz, the FBAR ADPLL provides a PVT-stable, high quality RF frequency reference for a range of low power, high data rate applications.