Title :
HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system
Author :
Duarte, D. ; Zepeda, P. ; Hsu, S. ; Maheshwari, A. ; Taylor, G.
Author_Institution :
Logic Technol. Developlment, Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes the design of a 1.2-mW, 0.027-mm2 thermal sensor and its accompanying supply voltage regulator, both implemented in a Hi-K, metal gate, 32nm technology. The designs incorporated built-in run-time variability reduction schemes for improved manufacturability, which allowed the sensor to achieve an INL of ±0.27°C over the operating range of 0°C to 110°C while the regulator met all functional specifications and introduced no additional yield loss. The DFT circuits needed to validate circuit performance in high volume manufacturing (HVM) are also described.
Keywords :
CMOS integrated circuits; design for manufacture; design for testability; detector circuits; temperature sensors; CMOS thermal sensor system; DFM technique; DFT circuits; HVM performance validation; built-in run time variability reduction; high volume manufacturing; power 1.2 mW; size 32 nm; supply voltage regulator; temperature 0 C to 110 C; Calculators; Layout; Regulators; Silicon; Temperature measurement; Thermal sensors; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617438
