Single event transient mitigation in cache memory using transient error checking circuits

Protecting a high performance radiation hardened by design (RHBD) cache from single-event transient (SET) induced peripheral circuit errors is presented. Cache memory holds processor architectural state and peripheral errors can cause incorrect operations that affect entire data words, including parity. Thus, a periphery circuit, e.g., word-line, error can be induced that results in silent data corruption, for instance by writing two locations at once. The design presented here includes checking circuits to detect potential SET induced errors, allowing mitigation by invalidation of the write-through cache blocks. A 16 kB cache and test engine, fabricated on an IBM 90 nm bulk CMOS process, irradiated with heavy ions, is used to provide experimental validation of the design.