Title :
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays
Author :
Geuskens, B. ; Khellah, M. ; Kulkarni, J. ; Karnik, T. ; De, V.
Author_Institution :
Circuit Res. Labs., Intel Labs., Hillsboro, OR, USA
Abstract :
Strained silicon has enhanced PMOS transistor current much more than NMOS. As such, IDSATN/IDSATP ≈ 1 is nearing reality. This work studies the effect of this presumably continuing trend on dual-port 8T bit cell performance. Preference for using NMOS or PMOS in write and read ports is shown to depend on current ratio, VMIN circuit assist and array access type.
Keywords :
MOS integrated circuits; elemental semiconductors; low-power electronics; silicon; NMOS; PMOS read and write port; PMOS transistor; low voltage dual-port 8T bit cell array; strained silicon; Computer architecture; Delay; MOS devices; Microprocessors; Noise; Noise robustness; Silicon;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617441
