Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction

This paper proposes an efficient method to predict the lifetime yield of analog circuits considering the joint effects of manufacturing process variations and parameter lifetime degradations. The method uses the idea of worst-case distance, which is an indicator of circuit robustness concerning process variations. The worst-case distance in circuit lifetime is predicted based on a new, quadratic prediction model in time domain. The lifetime yield of the circuit is obtained based on this quadratic model. We prove for the first time that the lifetime yield value is directly applicable to the calculation of reliability function and lifetime distribution of analog circuits, while previous modeling techniques either are only applicable for digital circuits, or require long simulation time. The experimental results show that the proposed method has an average error smaller than 5%, with a speed up of six times in comparison to an iterative optimization based lifetime yield analysis method.