HCW Keynote Address Holistic Design of Multi-Core Architectures

Summary form only given. Several forces are driving the market to put multiple execution cores on a single processor chip. But we cannot view (or design) those cores (and the connections between them) in the same way we did when we lived in a uniprocessor world. Previously, we expected each core to provide good performance on virtually any application, with energy efficiency, and without error or failure. Now that the level of interface with the user and the system is a multi-core chip, those requirements need only be met at the chip level - no single core need meet them. This provides the opportunity to think about processor architecture in whole new ways. This talk describes holistic design of a multi-core architecture - designing cores, caches, interconnect so that the chip as a whole provides maximum performance, high energy efficiency, and high performance per area. We discuss, in particular, on-chip heterogeneous multiprocessing and conjoined core architectures.