Title :
A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter
Author :
Balachandran, Ganesh K. ; Srinivasan, Venkatesh ; Rentala, Vijay ; Ramaswamy, Srinath
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A low-power jitter tolerant 2nd order active-passive continuous-time sigma-delta ADC in 65nm CMOS is presented. The use of just one active Gm-C integrator and a feed-forward path from the ADC´s input to the Gm´s output helps reduce power consumption. A FIR filter in the outermost feedback path reduces clock jitter impact. For a -2dBFS input, the ADC clocked at 300MHz achieves a 69dB SNR (10KHz - 1.2MHz BW) while consuming 1.16mW from a 1.4V supply.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital filters; low-power electronics; CMOS; FIR filter; active Gm-C integrator; active-passive continuous-time sigma-delta ADC; analog-digital converter; bandwidth 10 kHz to 1.2 MHz; clock jitter; continuous time ΣΔ ADC; feedforward path; frequency 300 MHz; low-power jitter tolerant; power 1.16 mW; size 65 nm; voltage 1.4 V; Clocks; Computer architecture; Finite impulse response filter; Jitter; Modulation; Noise; Resistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617455
