Title :
`Bottom-up´ learning, `top-down´ design for silicon systems
Author :
Bartlett, V.A. ; Morling, R.C.S. ; Kale, I.
Author_Institution :
Sch. of Electron. & Manuf. Syst. Eng., Polytech. of Central London, UK
Abstract :
At the Polytechnic of Central London (PCL), undergraduate level MOS VLSI design is taught through a 3-year BEng course of unusual structure, style and pacing. In this paper, an outline of the course is presented together with experiences relating to its delivery and associated full-custom and digital semi-custom student project work
Keywords :
MOS integrated circuits; VLSI; circuit CAD; educational courses; BEng course; MOS VLSI design; Polytechnic of Central London; bottom-up learning; circuit CAD; digital semi-custom; full-custom; silicon systems; student project work; top-down design; undergraduate level courses;
Conference_Titel :
Eurochip Project - VLSI Design in Higher Education, IEE Colloquium on
Conference_Location :
London
