A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in 0.18µm CMOS

This paper presents a pipelined MIMO detector designed for 4×4 16-QAM spatial multiplexing systems. A modified Dijkstra´s algorithm and a pre-calculation technique are proposed to improve the throughput up to 2.6Gb/s, and the Euclidean norm computation is approximated to reduce the chip area without degrading the error-rate performance. The entire detector occupies 1.56mm² in a 0.18μm CMOS process, and shows a near-optimal error-rate performance. In achieving a BER of 10-3, the performance of the proposed detector is only 0.1dB away from that of the optimal detection in terms of SNR.