HASP-1002: a hybrid wafer scale associative string processor

Author

Jalowiecki, I.P. ; Reche, J.J. ; Habiger, C. ; Lea, R.M.

Author_Institution

PolyCon, Tempe, AZ, USA

fYear

1992

fDate

22-24 Jan 1992

Firstpage

124

Lastpage

133

Abstract

The authors introduce and evaluate a multichip module produced in hybrid-WSI (wafer scale integration) technology embedded for real-time signal and data processing. The benefits and potential of the technologies of the HASP-1002 hybrid-WSI device are shown. The combination of improvements of the size-performance and the cost-performance trade-offs underlines the vitality of hybrid-WSI technologies, as traditionally the cost-performance trade-off worsens for size and weight sensitive applications

Keywords

CMOS integrated circuits; VLSI; digital signal processing chips; hybrid integrated circuits; microprocessor chips; modules; parallel architectures; real-time systems; HASP-1002; MCM; WASP; cost-performance trade-off; hybrid wafer scale associative string processor; hybrid-WSI; multichip module; wafer scale integration; Application specific processors; Control systems; Data processing; Los Angeles Council; Multichip modules; Packaging machines; Parallel processing; Real time systems; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-2482-5

Type

conf

DOI

10.1109/ICWSI.1992.171803

Filename

171803