VLSI design and implementation of a simple 4×4 Hopfield neural network

Several difficulties can arise when scaling up the size of a neural network; one is that the computational time can become prohibitive. One approach to scaling is to build accelerated hardware, such as customised VLSI circuits. Integrated circuits can provide some acceleration to the neural network computations and would, in addition, implement the network in an extremely compact form. This paper describes the first stage of implementation of a simple Hopfield neural network in VLSI, and was carried out as a final year undergraduate student design project at Liverpool University