Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC

Author

Philhower, R. ; Van Etten, J.S. ; Dabral, S. ; Nah, K. ; Greub, H. ; McDonald, J.F.

Author_Institution

Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

1992

fDate

22-24 Jan 1992

Firstpage

145

Lastpage

154

Abstract

A wideband thin-film wafer scale hybrid package (WSHP) or multi-chip module (MCM) will be used to interconnect the chips of a high-performance RISC (reduced instruction set computer) architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs heterojunction bipolar transistors (HBTs) and triple-level differential current-mode logic. Because of high power consumption yield limitations of the HBT technology, the processor is partitioned into multiple chips. These chips must be connected using lines capable of handling the fast rise-time signals. Also, the MCM must contain integrated bypass capacitors and termination resistors

Keywords

III-V semiconductors; VLSI; aluminium compounds; bipolar integrated circuits; gallium arsenide; heterojunction bipolar transistors; hybrid integrated circuits; metallisation; packaging; pipeline processing; reduced instruction set computing; thin film circuits; 1000 MIPS; GaAs-AlGaAs; HBT technology; HBTs; MCM; RISC; WSHP; fast rise-time signals; flip chips; heterojunction bipolar transistors; integrated bypass capacitors; multi-chip module; multichip modules; multiple chips; power consumption; reduced instruction set computer; semiconductor; termination resistors; triple-level differential current-mode logic; wafer scale hybrid package; wafer-scale interconnections; wideband interconnects; yield limitations; Capacitors; Chip scale packaging; Computer aided instruction; Computer architecture; Energy consumption; Gallium arsenide; Heterojunction bipolar transistors; Logic; Reduced instruction set computing; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-2482-5

Type

conf

DOI

10.1109/ICWSI.1992.171805

Filename

171805