Design and evaluation of wafer scale clock distribution

The authors describe a computer program which is used for simulating the performance of large wafer scale integration clock distribution networks, made up of both passive transmission line elements and active buffers. The theoretical basis for the model is briefly reviewed. The authors present several example networks for 4-in wafers, comparing the AC performances as a function of power dissipation, layout area, and harvesting yield. The sensitivity of performance (as measured by propagation delays and clock skew) to random or systematic process-related fluctuations and defects is calculated using the model. A new measurement system is introduced for electrically characterizing the performance of clock distribution networks on fabricated wafers and within multichip modules