A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology

This paper presents a 2.5-8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear equalizer (LEQ) and decision feedback equalizer (DFE) are used to eliminate ISI effect, compensate channel loss, and improve BER performance for 28-inch FR4 channel. The 3-tap feed-forward equalizer (FFE) is used to improve signal quality in transmitter. The resolution of de-emphasis and pre-shoot is up to 1/63 and 1/15. It also performs 0.8UIpp eye opening for 8Gb/s operation. A 2^nd order clock and data recovery (CDR) employs digital finite state machine to track phase difference and frequency between clock and data. The CDR can cover 0 to -5000ppm frequency offset of SSC modulation and achieve jitter tolerance of up to 0.2UIpp at 8Gb/s with a BER=10^-10 when all specified jitter sources is included. The integrated transceiver operates from 2.5Gb/s to 8Gb/s and consumes 235mA at 8Gb/s current with 0.95V supply voltage. The test-chip is implemented by flip chip layout and fabricated in TSMC 40nm 0.9V/1.8V CMOS technology. The area of transceiver is 725um × 615um.