DFGs for synthesis of alternative architectures: Node activation synthesis

High-level synthesis systems are becoming one of the necessary standards in digital design of complex architectures since they allow a high degree of freedom to the designers in exploring and evaluating architectural alternatives. This possibility is particularly interesting when complex VLSI/WSI (wafer scale integration) architectures are considered. Synthesis and evaluation of alternative architectures is performed, adopting the data flow graph (DFG) model. In particular, the problem of optimal scheduling of node activities and delay minimization is examined. Procedures for graph balancing and optimal delay distribution are provided. The balancing and minimization procedures proposed identify the optimal scheduling for node activation synthesis both in terms of the timing parameters proper to the graph (latency and throughput) and in terms of the amount of delay added to the arcs to grant correct synchronization