DocumentCode
2789051
Title
Critical area analysis
Author
Walker, D.M.H.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1992
fDate
22-24 Jan 1992
Firstpage
281
Lastpage
290
Abstract
The critical area is the region on an integrated circuit where the occurrence of a catastrophic spot defect will cause a functional circuit fault. The author describes how to efficiently compute detailed critical areas with the VLASIC Monte Carlo yield simulator. Methods for reducing the computational cost are described, along with some application examples. An SRAM cell failure caused by an extra second metal defect is analyzed as an example
Keywords
Monte Carlo methods; SRAM chips; VLSI; digital simulation; failure analysis; integrated circuit testing; SRAM cell failure; VLASIC Monte Carlo yield simulator; catastrophic spot defect; computational cost; critical area; functional circuit fault; second metal defect; Circuit faults; Circuit simulation; Computational modeling; Conducting materials; Design optimization; Monte Carlo methods; Redundancy; Statistics; Wires; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-2482-5
Type
conf
DOI
10.1109/ICWSI.1992.171820
Filename
171820
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