Title :
An enhanced one-step C-testable design of two-dimensional iterative logic arrays
Author :
Kim, Jung H. ; Sung, Hongki
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
The authors present an improved approach to one-step C-testability of orthogonal two-dimensional iterative logic arrays. This is an improvement of the approach of W. Huang and F. Lombardi (1988) and H. Elhuni et al. (1986). A group of sufficient conditions to test two-dimensional iterative logic arrays with a constant number of test vectors independent of the array size (C-testability) is stated. It is proved that the proposed approach requires a smaller number of test vectors than in previous works
Keywords :
iterative methods; logic arrays; logic testing; array size; one-step C-testable design; orthogonal arrays; test vectors; two-dimensional iterative logic arrays; Digital signal processing; Fault diagnosis; High performance computing; Iterative methods; Logic arrays; Logic design; Logic testing; Sufficient conditions; Very large scale integration; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-2482-5
DOI :
10.1109/ICWSI.1992.171825
