Efficient fault diagnosis of switches in wafer arrays

Considers an abstract model of a wafer-scale system where functional modules are connected by connections which run over wiring channels. Programmable switches are located at the junction of these wiring channels. The proposed technique is based on recursively finding progressive fault-free paths across regions of the wafer whose boundaries have been diagnosed to be fault-free. It is shown that such a technique will work with high probability and could be performed in time polynomial in the size of the array. The division of the wafer requires paths of short lengths and it is shown that these paths exist with high probability