Title :
Optimal design of megabyte second-level caches for minimizing bus traffic in shared-memory shared-bus multiprocessors
Author :
Oyang, Yen-Jen ; Wu, Le-Chun
Author_Institution :
Dept. of Comput. Sci., & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
As the design of shared-memory shared-bus multi-processors is heading toward employing megabyte second-level caches, how to optimize the design of the second-level caches in order to minimize the traffic on the shared bus and thus improve the system scalability is of great interest. The paper presents a comprehensive study on this issue through extensive trace-driven simulations and concludes with a few general and effective rules
Keywords :
buffer storage; multiprocessing systems; parallel architectures; bus traffic; megabyte second-level caches; shared bus; shared-memory shared-bus multiprocessors; system scalability; trace-driven simulations; Computer science; Context modeling; Councils; Design engineering; Design optimization; Multitasking; Scalability; Scheduling; Switches; Throughput;
Conference_Titel :
System Sciences, 1992. Proceedings of the Twenty-Fifth Hawaii International Conference on
Conference_Location :
Kauai, HI
Print_ISBN :
0-8186-2420-5
DOI :
10.1109/HICSS.1992.183196
