DocumentCode :
2789252
Title :
Design of VLSI implementation-oriented LDPC codes
Author :
Zhong, Hao ; Zhang, Tong
Author_Institution :
Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
Volume :
1
fYear :
2003
fDate :
6-9 Oct. 2003
Firstpage :
670
Abstract :
Recently, low-density parity-check (LDPC) codes have attracted much attention because of their excellent error-correcting performance and highly parallelizable decoding scheme. However, the effective VLSI implementation of an LDPC decoder remains a big challenge and is a crucial issue in determining how well we can exploit the benefits of the LDPC codes in real applications. In this paper, following the joint code and decoder design philosophy, we propose a semi-random design scheme to construct the LDPC codes that not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations. The corresponding partially parallel decoder has a very regular structure and simple control mechanism. Our computer simulations show that such LDPC codes achieve very good performance comparable to their counterparts constructed in a fully random scheme, which however have little chance of fitting to partially parallel decoder implementations.
Keywords :
VLSI; decoding; error correction codes; parallel architectures; parity check codes; LDPC codes; VLSI implementation; error-correcting codes; low-density parity-check codes; parallel decoding schemes; partially parallel LDPC decoder; Bipartite graph; Computer errors; Computer simulation; Concurrent computing; High performance computing; Iterative decoding; Message passing; Parity check codes; Systems engineering and theory; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Vehicular Technology Conference, 2003. VTC 2003-Fall. 2003 IEEE 58th
ISSN :
1090-3038
Print_ISBN :
0-7803-7954-3
Type :
conf
DOI :
10.1109/VETECF.2003.1285102
Filename :
1285102
Link To Document :
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