Managing dynamic reconfiguration on MIMO Decoder

This paper is about the implementation of a MIMO V-BLAST (vertical bell laboratories layered space-time) square root decoder in a FPGA using dynamic partial reconfiguration. The decoder architecture is based on four CORDIC (coordinate rotation digital computer) units. Among these CORDIC units, three are used in rotation mode and the fourth one is used in vectoring mode. The design implementation aims power saving and area efficiency allowing dynamically changing the interconnections between the fixed modules in the reconfigurable modules. This MIMO square root design method shows the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.