Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

In this paper, a method is proposed that corrects RTL designs and builds on the sequential equivalence checking technique developed by the authors in [2], where the specification and the implementation are converted into High-Level Decision Diagrams (HLDD) [1]. In order to apply the proposed design error correction method, a certain degree of structural correspondence between the specification and the implementation at the level of circuit variables should be provided. Its application can be seen in engineering change applications where a part of an RTL implementation is altered.