DocumentCode
2790641
Title
Designing Efficient Asynchronous Memory Operations Using Hardware Copy Engine: A Case Study with I/OAT
Author
Vaidyanathan, K. ; Huang, W. ; Chai, L. ; Panda, D.K.
Author_Institution
Comput. Sci. & Eng., Ohio State Univ., Columbus, OH
fYear
2007
fDate
26-30 March 2007
Firstpage
1
Lastpage
8
Abstract
Memory copies for bulk data transport incur large overheads due to CPU stalling, small register-size data movement, etc. Intel´s I/O Acceleration Technology offers an asynchronous memory copy engine in kernel space which alleviates such overheads. In this paper, we propose a set of designs for asynchronous memory operations in user space for both single process (as an offloaded memcpy()) and lPC using the copy engine. We analyze our design based on overlap efficiency, performance and cache utilization. Our microbenchmark results show that using the copy engine for performing memory copies can achieve close to 87% overlap with computation. Further, the copy engine improves the copy latency of bulk memory data transfers by 50% and avoids cache pollution effects. With the emergence of multi-core architectures, the support for asynchronous memory operations holds a lot of promise in reducing the gap between the memory and processor performance.
Keywords
cache storage; data communication; memory architecture; DMA; Intel I/O Acceleration Technology; asynchronous memory operation; bulk memory data transfer; cache storage; hardware copy engine; inter-process communication; multicore architecture; Acceleration; Computer architecture; Delay; Engines; Hardware; Kernel; Linear predictive coding; Performance analysis; Pollution; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
Conference_Location
Long Beach, CA
Print_ISBN
1-4244-0910-1
Electronic_ISBN
1-4244-0910-1
Type
conf
DOI
10.1109/IPDPS.2007.370479
Filename
4228207
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