• DocumentCode
    2790702
  • Title

    Modeling non-slicing floorplans with binary trees

  • Author

    Balasa, F.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
  • fYear
    2000
  • fDate
    5-9 Nov. 2000
  • Firstpage
    13
  • Lastpage
    16
  • Abstract
    Several novel topological representations of non-slicing floorplans have been more recently proposed, providing new ideas and techniques for solving block placement problems and other related layout applications. Among these topological representations, ordered trees exhibit a lower redundancy and, therefore, a provable smaller search space, which makes them the best topological candidate for solving general block placement problems. Starting from the early eighties, binary trees have been widely used to represent slicing floorplans. This paper shows that binary trees can efficiently model non-slicing floorplans as well, as there is a one-to-one mapping between the sets of binary and ordered trees representing the floorplan. Moreover, this paper shows that binary trees exhibiting a certain property can be used to represent block placement configurations with symmetry constraints, which is very useful when dealing with device-level placement problems for analog layout. As the number of these trees is proven to be smaller than the number of symmetric-feasible sequence-pairs, using binary trees is better than using either sequence-pairs or O-trees when solving analog placement problems. A comparative evaluation, substantiating these theoretical results, has been carried out by providing alternative optimization engines to a placement tool operating in an industrial environment.
  • Keywords
    circuit layout CAD; simulated annealing; binary trees; block placement; block placement configurations; device-level placement problems; non-slicing floorplans modelling; one-to-one mapping; ordered trees; symmetry constraints; Binary trees; Constraint optimization; Constraint theory; Cost function; Engines; Genetic algorithms; Integrated circuit layout; Simulated annealing; Space exploration; Vegetation mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-6445-7
  • Type

    conf

  • DOI
    10.1109/ICCAD.2000.896443
  • Filename
    896443