Title :
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
Author :
Okuma, Yasuyuki ; Ishida, Koichi ; Ryu, Yoshikatsu ; Zhang, Xin ; Chen, Po-Hung ; Watanabe, Kazunori ; Takamiya, Makoto ; Sakurai, Takayasu
Author_Institution :
Semicond. Technol. Acad. Res. Center (STARC), Yokohama, Japan
Abstract :
Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO´s, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
Keywords :
CMOS integrated circuits; logic circuits; voltage regulators; CMOS; current 2.7 muA; current 200 muA; digital LDO; digital circuit; energy efficiency; logic circuit; low drop out regulator; size 65 nm; voltage 0.45 V; voltage 0.5 V; Bidirectional control; CMOS integrated circuits; Clocks; Current measurement; Shift registers; Switches; Transient analysis;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617586
