An associative processor array as part of a heterogeneous vision architecture

A heterogeneous vision architecture is introduced which aims to satisfy the computing demands of real-time computer vision by providing parallelism in three different forms. A pipeline of digital signal processing chips is used for initial signal processing, a SIMD associative processor array for image processing and feature extraction tasks and a MIMD network of transputers for parallel processing of extracted objects. The paper describes GLiTCH, the associative processor array to be used and the novel processing modes available due to the use of content addressable memory. The means of performing inter-processor communication are described for both regular and irregular connectivity patterns. The VLSI implementation of the GLiTCH chip, containing sixty-four processing elements is described and some performance estimates are given